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Welcome to HOPE <Version 2.0>!

HOPE is a fault simulator for synchronous sequential circuits.
It employs the parallel fault simulation technique and employs
several heuristics to reduce the parallel fault simulation time.

HOPE was developed in the Bradley Department of Electrical
and Computer Engineering, Virginia Polytechnic Institute & State University
(VPI&SU) and the copy right belongs to VPI&SU.
The source code is released for teaching and research use only. 
Any publication in which HOPE was used to obtain the results should
cite the reference given below. (Please do not say that a public domain
tool was used in this research.)
 
This program, or any derivative thereof, may not be reproduced
nor used for any commercial product without a written permission form
from Prof. Dong S. Ha. For commercial use of HOPE or if any bugs found, 
please contact to
 
        Prof. Dong S. Ha
        Department of Electrical and Computer Eng.
        Virginia Tech
        Blacksburg, VA 24061
 
        Ph.: (540) 231-4942
        Fax: (540) 231-3362
        E-Mail: ha@vt.edu
        Web: http://www.ee.vt.edu/ha

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REFERENCES:
   [1] H. K. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault Simulator
       for Synchronous Sequential Circuits," IEEE Transactions on Computer-
       Aided Design of Integrated Circuits and Systems, Vol. 15, No. 9,
       pp. 1048- 1058, September 1996.

   [2] H. K. Lee and D. S. Ha, "New Methods of Improving
       Parallel Fault Simulation in Synchronous Sequential Circuits,"
       Proc. International Conference on Computer-Aided Design,
       pp. 10-17, Oct. 1993.

   [3] H. K. Lee and D. S. Ha, "HOPE: An Efficient Parallel Fault
       Simulator for Synchronous Sequential Circuits," Proc. 29th
       Design Automation Conference, pp. 336-340, June 1992.
